EC2314 DIGITAL SIGNAL PROCESSING IMPORTANT QUESTION

EC2314 DIGITAL SIGNAL PROCESSING IMPORTANT QUESTION


UNIT-1

2 MARK

1.Power (or)Energy Signal
2.stability

16 Mark

11 A) linear and non-linear and  Time varient or invarient
or
11 B) Advantage of DSP and Application of DSP


UNIT -II

2 Mark

1.Initial value theorem
2.Final value theorem

16 Mark

1. Find inverse Z-transform long division
           i) Partial fraction method
           ii) Residue method
           iii) Convolution method


UNIT -III

2 Mark

1. Difference between DTFT with DFT

16 Mark

1. DIF FFT (Butterfly diagram)
2. DIT FFT (Butterfly diagram)

UNIT-IV

16 Mark

1.Handling window/hamming window
 or
2. Buffer with chebysher filter(Sum)

UNIT -V

16 Mark

1. TMS  architecture

REJINPAUL IMPORTANT QUESTION

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Note:
 studying above questions thoroughly you get pass mark but to get higher marks study  according to syllabus


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CS2311 OBJECT ORIENTED PROGRAMMING IMPORTANT QUESTION

Rejinpaul important  question for object oriented programming-CS2311

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EE2303 TRANSMISSION AND DISTRIBUTION

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EE2302 REJINPAUL IMPORTANT QUESTION FOR ELECTRIC MACHINES II

Rejinpaul important  question for Electrical machines II -EE2302

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OOPS LAB CS2312 SET QUESTION ANSWERS FOR EEE

                                                                                  Anna university
                                                    Departement of Electrical and Electronics Engineering
                                                       CS2312- Object Oriented Programming laboratory
                                                                               Regulation-2008
Set question answer

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REJINPAUL IMPORTANT QUESTION FOR DIGITAL LOGIC CIRCUITS

Anna University Exams May/June 2014 Regulation 2008

Rejinpaul.com Important Questions 4th Semester BE/BTECH

EE2255 Digital Logic Circuits

1. Obtain the minimum sop using QUINE- McCLUSKY method and verify using K-map
F=m0+m2+m4+m8+m9+m10+m11+m12+m13
2. Reduce the Boolean function using k-map technique and implement using gates f (w, x, y, z)= _m (0,1,4,8,9,10) which has
the don’t cares condition d (w, x, y, z)= _m (2,11)
3. Implement the Boolean function using 8:1 mux. (8 marks) F (A, B, C, D) =A’BD’+ACD+B’CD+A’C’D.
4. Design A Full Adder And A Full Subtractor.
5. Simplify the following Boolean functions by using K’Map in SOP & POS. F (w, x, y, z) = _m (1, 3, 4, 6, 9, 1, 12, 14)
6. Design a 4-bit binary to excess-3 converter using the unused combinations of the code as don’t care
conditions. Represent the converter using logic diagram.
7. A sequential circuit has 2D ff’s A and B an input x and output y is specified by the following next state and output equations.
A (t+1)= Ax + Bx B (t+1)= A’x
Y= (A+B) x’
(i) Draw the logic diagram of the circuit. (ii)Derive the state table. (iii)Derive the state diagram.
8. Design a mod-10 synchronous counter using Jk ff. write excitation table and state table.
9. Write the excitation tables of SR, JK, D, and T Flip flops (8 marks) b) Realize D and T flip flops using Jk flip flops
10. Design a sequential circuit using JK flip-flop for the following state table [use state diagram]
11. Design a counter with the following repeated binary sequence:0, 1, 2, 3, 4, 5, 6.use JK Flip-flop.
12. Design an asynchronous sequential circuit that has 2 inputs x2 and x1, and one output z. the output is to remain 0 as long as an X1
is 0. The first change in x2 that occurs while x1 is 1 will cause z to be 1. Z is to remain 1 until x1 returns to 0. Construct a state
diagram and flow table. Determine the output equations.
13. Obtain the primitive flow table for an asynchronous circuit that has 2 input’s x, y and
output z. an output z=1, is to occur only during the input state xy=01 and then if and only if the input state xy=01 is preceded
by the input sequence xy=01, 00, 10, 00, 10, 00
14. Design a circuit with input a and b to give an output z=1 when AB =11 but only if A becomes 1 before B, by drawing total state
diagram, primitive flow table and output map in which transient state is included.
15. Design an Asynchronous sequential circuit using SR latch with two inputs A and B and one output y. B is the control input
which, when equal to 1, transfers the input A to output y. when B is 0, the output does not change, for any change in input.
16. Explain in detail about PLA with a specific example.
17. Explain with neat diagrams RAM architecture
18.Implement the following function using PLA. A (x, y, z) = m (1, 2, 4, 6)
B (x, y, z) = _m (0, 1, 6, 7) C (x, y, z) = _m (2, 6)
19. Discuss on the concept of working and applications of following memories.
ii) ROM II)EPROM iii)PLA.
20. compare the various digital logic families.
21. Write notes on FPGA.
22. Write notes on the characteristics and implementation of the following digital logic families.
(i)ECL ii) TTL
23. Write a HDL code for state machine to BCD to ex–3 codes Converter.
24. Write a behavioral VHDL description of the 4 bit counter.
25. Write VHDL code for a full sub tractor using logic Equation
26. Write a VHDL description of an S-R latch using a process
27. Write a HDL code for 8:1 MUX using behavioral model
28. Write the HDL description of the circuit specified by the Following Boolean equations
S = xy ‘+ x’ y C=xy

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